CS 507 Schedule

• September 15: We will have a discussion of memory-level parallelism and how exploiting it can help improve performance in large instruction window processors. Our main paper comes from the latest ISCA: please read A Case for MLP-Aware Cache Replacement by M.K. Qureshi, D.N. Lynch, O. Mutlu, and Y.N. Patt in ISCA 2006.

  Our discussion will also include the following supplementary papers. Please read:

  • MLP Yes! ILP No! by Andy Glew in the abstracts of the Wild and Crazy Ideas session at ASPLOS 1998.
  • Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors by O. Mutlu, J. Stark, C. Wilkerson and Y.N. Patt in HPCA 2003.
  • Microarchitecture Optimizations for Exploiting Memory-Level Parallelism by Y. Chou, B. Fahs and S. Abraham in ISCA 2004.
  • Kilo-instruction Processors: Overcoming the Memory Wall by A. Cristal, O.J. Santana, F. Cazorla, M. Galluzzi, T. Ramírez, M. Pericàs and M. Valero in IEEE Micro 25(3) May 2005.
• September 21:
  Main paper: Prophet/Critic Hybrid Branch Prediction, Falcón et al., ISCA 2004

  Supplemental readings:

  • Reconsidering Complex Branch Predictors, Jiménez, HPCA 2003.
  • Alternative Implementations of Hybrid Branch Predictors, Chang et al., MICRO 1995.
  • Confidence Estimation for Speculation Control, Grunwald et al., ISCA 1998
• September 28:
  Main paper: Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization, by Amir Roth, ISCA 2005

  Supplemental readings:

  • The Wikipedia page on Bloom Filters
  • Scalable Hardware Memory Disambiguation for High ILP Processors by Sethumadhavan et al. MICRO 2003
  • Dynamic Instruction Reuse by Sodani and Sohi, ISCA 1997
  • Reducing Design Complexity of the Load/Store Queue by Park et al., MICRO 2003
  Assignment: Project Proposal
• October 5: To be announced Individual meetings with:
  • 1:30pm (open)
  • 2:00pm Desiree Ottoni
  • 2:30pm Wei Chen
  • 6:40pm Thomas Uphill
  • 7:10pm John-Austen Francisco
  • 7:40pm Mohammad Tanvir Alam
  • 8:10pm John McCabe
  • 8:40pm (open)
• October 12: Thomas Uphill presents: Learning-Based SMT Processor Resource Distribution via Hill-Climbing by Choi and Yeung from ISCA 2006.
  Supplemental readings:
  • Simultaneous Multithreading: Maximizing On-Chip Parallelism by Tullsen et al., ISCA 1995.
  • Dynamically Controlled Resource Allocation in SMT Processors by Cazorla et al., MICRO 2004.
  • Handling Long-latency Loads in a Simultaneous Multithreading Processor by Tullsen and Brown, MICRO 2001.
  • Hyper-Threading Technology Architecture and Microarchitecture by Marr et al., Intel Technology Journal, 2002.
• October 19: No class
• October 26: Desiree Ottoni presents An Ultra Low Power System Architecture for Sensor Network Applications by Hempstead et al. in ISCA 2005.
  Supplemental readings:
  • Hardware Design Experiences in ZebraNet by Zhang et al. in SenSys 2004
  • An Ultra Low-Power Processor for Sensor Networks by Ekanayake et al. in ASPLOS 2004
  • A Second-Generation Sensor Network Processor with Application-Driven Memory Optimizations and Out-of-Order Execution by Nazhandali et al. in CASES 2005
• November 2: John McCabe presents:
  From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation by Yehia and Temam, ISCA 2004
  Supplemental readings:
  • Serialization-Aware Mini-Graphs: Performance with Fewer Resources by Bracy and Roth, MICRO 2006
  • An Approach for Implementing Efficient Superscalar CISC Processors by Hu et al., HPCA 2006
  • Understanding the Differences Between Value Prediction and Instruction Reuse by Sodani and Sohi, MICRO 1998
• November 9: John-Austen Francisco presents SODA: A Low-power Architecture for Software Radio by Lin et al. in ISCA 2006.
  Read John-Austen's tutorial.
  Supplemental readings:
  • Performance of Iterative Multiuser Decoding and Channel Estimation in WCDMA systems by Bhashyam and Hottinen, Vehicular Technology Conference Proceedings (VTC), 2000.
  • A novel multipath searcher implementation for WCDMAreceivers by Grayver et al., ISCAS 2004.
  • Design and Implementation of ConfigurableW-CDMA Rake Receiver Architectures on FPGA by Chugh et al., IPDPS 2005.
• November 16: Tanvir presents Interconnect-Aware Coherence Protocols for Chip Multiprocessors by Cheng et al. in ISCA 2006.
  Supplemental papers:
  • Managing Wire Delay in Large Chip-Multiprocessor Caches by Beckmann and Wood, MICRO 2004
  • A NUCA Substrate for Flexible CMP Cache Sharing by Huh et al. in ICS 2005
  • Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches by Kim, Burger and Keckler in MICRO Top Picks 2003
• November 23: No class (Thanksgiving)
• November 30
  Read at least four of the following papers from this year's (upcoming) MICRO. Skim all of them. We'll have an interesting discussion.
  
  • Support for High-Frequency Streaming in CMPs, Rangan et al., MICRO 2006
  • Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths, Kim et al., MICRO 2006
  • Head and Tail Duplication for Convergent Hyperblock Formation, Maher et al., MICRO 2006
  • Dataflow Predication, Smith et al., MICRO 2006
  • An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget, Isci et al., MICRO 2006
  • Live, Runtime Phase Monitoring and Prediction on Real Systems with Application to Dynamic Power Management, Isci et al., MICRO 2006
  • Memory Prefetching Using Adaptive Stream Detection, Hur and Lin, MICRO 2006
  • Die Stacking (3D) Microarchitecture, Black et al., MICRO 2006
• December 7: Wei Chen presents: A Robust Main-Memory Compression Scheme by Ekman and Stenstrom, ISCA 2005
  Supplemental readings:
  • Frequent Value Locality and Value-Centric Data Cache Design by Zhang et al. in ASPLOS 2000
  • Adaptive Cache Compression for High-Performance Processors by Alameldeen and Wood, ISCA 2004